As portable computer applications proliferate, it has been desirable to incorporate power management techniques into microprocessors to reduce power and extend the battery life of the portable computer. One power management technique entails shutting down the microprocessor while statically maintaining code. This state is called low power stop (LPSTOP), where the microprocessor is completely quiescent, using no power. In portable applications, it is desirable to be able to force microprocessors in and out of this low power state (LPSTOP) very rapidly. Historically, the largest performance penalty in cycling in and out of LPSTOP has been the amount of time the phase-locked loop (PLL) requires to re-acquire phase lock. Thus, the frequency at which the microprocessor can use the low power state is dictated by how fast a PLL can acquire (re-acquire) phase-lock. Slow lock times reduce the frequency of entering/leaving LPSTOP and result in increased power dissipation. Fast lock times increase the frequency of entering LPSTOP and, therefore, reduce power.
In an analog PLL a voltage-controlled oscillator (VCO) is used to generate a periodic signal that is "locked" to a reference clock. This type of phase-locked loop combines frequency and phase lock into one mechanism. The frequency and phase of the VCO are modulated by an analog voltage adjusted via feedback mechanisms. The feedback mechanism is generally supplied from a sequential phase/frequency detector. The sequential phase/frequency detector outputs an "up" or "down" pulse proportional to phase error width and in the direction to pull in the frequency and phase of the VCO output signal to that frequency and phase of the target reference clock signal. When acquiring phase, frequency and phase constantly overshoot the target, but the magnitude of overshoot is slowly reduced until it is within acceptable limits. At this point the PLL is considered locked. For the above reasons, this type PLL suffers unnecessary time penalties on phase and frequency acquisition.
The gain of a VCO is defined as dF/dV (the change in VCO frequency per change in the analog control voltage). In a PLL, gain is a sensitive parameter; a high gain provides for faster phase acquisition but at the expense of stability. A low gain has very slow phase acquisition, but provides greater stability in normal clocking environments; however, a low gain VCO may not be able to track frequency drift or frequency modulation. One measure of a PLL's stability is measured by its ability to maintain minimal skew between the two signals it is phase-locking. Thus, it is desirable to have a PLL that provides for a very fast phase acquisition and improved long term stability.